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STV0974
Mobile Imaging DSP
Features
Supports VS6552 - 640 x 480 (VGA) color CMOS image sensor Supports VisionLink low EMI link to image sensor Specialized video processor for noise/defect filtering, color reconstruction, sharpness enhancement and radial corrections Programmable gamma correction for LCD support Programmable cropping, down-sizing by 1.5, 2, 2.5, 3, 4, 5 and 6, MMS (Multi Media Messaging Service) digital zoom JPEG compression, with programmable target file size M-JPEG operation at up to 30 frame/s at VGA resolution Programmable pixel output format including ITU-R 656 modes, RGB viewfinder modes and JPEG baseline Flashgun control Flexible host interface:
Description
The STV0974 is a low power digital image processor designed for the VS6552 color VGA image sensor. The STV0974 uses advanced image processing techniques to deliver high quality VGA images at up to 30 frames per second (frame/s). The sensor data received via the low EMI sensor interface is processed in real time: this includes pixel defect correction, color interpolation, image sharpness enhancement, selective noise filtering, cropping and scaling, allowing digital zoom for ViewFinder or MMS applications. Finally the image can be JPEG-compressed in real-time. The STV0974 also performs sensor housekeeping functions such as automatic exposure and white balance controls.
Applications
Mobile phone embedded camera system PDA embedded camera or accessory camera Wireless security camera
Technical Specifications
Sensor Frame rate (frame/s) Power supply Power requirements Package dimensions Temperature range 640 x 480 color CMOS (VS6552) up to 30 1.8 +/- 0.1 V 110 mW active < 30 W standby 6 mm x 6 mm x 1.2 mm [ -25; +70 ] C
8-bit data /Hsync /Vsync video output interface and IC camera control interface 8-bit microprocessor interface with 2 Kbyte video FIFO for JPEG data, 10 Kbyte for nonJPEG data, interrupt and DMA requests
Multi-mode exposure control and color balance 30 W ultra low-power standby 6 x 6 mm TFBGA low-footprint & lead-free package
Ordering Information
Ordering code
STV0974/TR STV0974E/TR
Package
TFBGA SnPb balls TFBGA AFOP lead-free balls
Rev. 3 November 2004 1/69
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STV0974
Contents
Chapter 1
1.1 1.2 1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Viewfinder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Still features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Live features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2 Chapter 3 Chapter 4
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Video processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Video compression (VC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Video output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Camera control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 5
5.1 5.2 5.3 5.4 5.5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 6
6.1 6.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 7
PCB layout guide lines for the STV0974 and VS6552 . . . . . . . . . . . . . . . . . . . .64
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STV0974 Chapter 8 Chapter 9 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Evaluation kit and demonstration boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
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STV0974
Overview
1
Overview
The STV0974 is a mobile imaging digital signal processor which, when used with VS6552 CMOS color VGA image sensor from STMicroelectronics, performs all the required data processing to deliver good quality Viewfinder, still and live color images. The STV0974 performs high quality color processing on images, achieving JPEG compression if requested and transfers them to a baseband through one of the available interfaces. Data is transferred from sensor to STV0974 through Low Electromagnetic Interference (EMI) interface, using the sensor data transfer protocol over LVDS. Data is transferred from STV0974 to Baseband
through the video output interface. In video mode, the processor streams video data in a format which closely follows the data format specified in the ITU-R656 standard. through the microprocessor Interface. In microprocessor mode, the video data is stored in a small FIFO before is it pulled out of the asynchronous microprocessor interface by the host system (with DMA support).
1.1
Viewfinder mode
When connected to microprocessor interface or video output interface, the STV0974 can process Viewfinder image up to 30 frame/s.
1.2
Still features
When requested by the baseband, the STV0974 captures bayer data from the sensor. Data is then color processed, down-scaled and/or compressed and sent through video output or microprocessor interface. In still mode, the first image produced has a guaranteed good exposure and color balance for single shot capture.
1.3
Live features
When connected to microprocessor interface or video output interface, the STV0974 can process live video up to 30 frame/s and eventually proceed to down-scaling and compression with on-chip Motion JPEG. Live mode is intended for capture of video sequences.
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Functional block diagram
STV0974
2
Functional block diagram
Figure 1: Functional block diagram
POR RST CLK PDN
Clock & Power management
SCL RAM - ROM Microprocessor I2C slave SDA
Internal bus PCLKP Sensor interface PCLKN PDATAP PDATAN MSCL MSDA VisionLink serial receiver VC VP
Parallel interface and FIFO
Mux
DIO[0:13]
I2C master
Video output interface
STV0974
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STV0974
Signal description
3
Signal description
Table 1: STV0974 signal description Pin name
Power supplies VDD VCORE VDDPOR VSS Sensor interface PDATAP, PDATAN PCLKP, PCLKN MSDA MSCL Host interface POR RST CLK PDN DIO[0:11]DIO[13] DIO[12] SDA SCL Test interface (ST internal use) TMS TCK TDI TDO Not connected NC Not connected I I I O Test mode Test clock Test data in Test data out O I I I I/O I/O I/O I/O Power on reset output Reset input System clock Power down Host interface configurable I/O, see Table 2 Flash Strobe Output (FSO) Host I2C data Host I2C clock subLVDS In subLVDS In I/O I/O Sensor data +, sensor data -, with internal 100 termination resistor Sensor clock +, sensor clock -, with internal 100 termination resistor Sensor I2C data Sensor I2C clock PWR PWR PWR PWR Positive power supply Decoupling for internal core power supply Power on reset VDD supply 1.8 V Digital ground
Type
Description
Table 2: Host interface pins - output modes Pin name
DIO[0:7] DIO[8] DIO[9] DIO[10] DIO[11] DIO[12] DIO[13]
Microprocessor interface
DATA[0:7] RS CSN WRN RDN DRQ IRQ
Video port
DATA[0:7] HSYNC VSYNC HCLK NC FSOa NC
a. Flash Strobe Output
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Functional description
STV0974
4
4.1
Functional description
Overview
The processor includes a chain of dedicated video data processing blocks controlled by a microprocessor. The processing blocks perform the main video pipe processing while the microprocessor manages the interactions between the sensor, the functional blocks and the host. The host controls and monitors the STV0974 via a set of read/write registers accessible via the I2C interface for the streaming video mode and via the asychronous microprocessor interface for the microprocessor mode. In video mode, the processor streams video data in a format which closely follows the data format specified in the ITU-R656 standard. In microprocessor mode, the video data is stored in a small FIFO before is it pulled out of the asynchronous microprocessor interface by the host system (with DMA support).
4.1.1
Video pipe block description
Please refer to the block diagram (Figure 1). Sensor interface This block decodes the incoming serial data stream from the sensor (raw bayer data) and converts it into a parallel form for the processing chain. Video processor The video processor converts the raw bayer data from the sensor to RGB or YUV processed data by applying a number of filters to the data then scaling and converting the data into either one of the RGB modes or into YUV mode. Video JPEG compressor The video compressor converts the processed data from the video processor and converts the data into JPEG format. The compression ratio applied to the image can be controlled by the microprocessor. Streaming video output port In streaming video mode the data from either the video processor or the video compressor is enclosed in a format which closely follows the data format specified in the ITU-R656 standard. Microprocessor interface In microprocessor interface mode, the data from the video processor or video compressor is stored in a FIFO. The interface informs the system via an IRQ or a DRQ that the FIFO is filling up. The system then has to pull some of the data from the STV0974 via the microprocessor interface.
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STV0974 4.1.2 Control
Functional description
Register map The STV0974 is controlled via a register map that is maintained by the STV0974 microprocessor. Each register in the map has an address and contains either read or read/write data. The read only registers detail the current state of the STV0974. Read/write registers can be written to in order to modify the default behavior of the STV0974. The map is accessed via I2C or via the microprocessor interface. Micro processor interface In microprocessor interface mode the STV0974 register map can be accessed by writing the address of the register to the port and then reading or writing the register value. Video output interface In streaming video mode, the STV0974 register map can be accessed via the I2C port on the STV0974. The STV0974 is addressed by supplying the device address, register address and value to be written or read. Microprocessor The microprocessor maintains the system interface via the register map. Any changes in system state are reflected in this map by the microprocessor and any changes commanded by the host system via this interface are then applied by the microprocessor. When the system is commanded to change state, the microprocessor configures the functional blocks from the STV0974 and the sensor into the requested mode. The register map is updated accordingly to reflect the new state of the hardware. The microprocessor monitors statistics gathered from the incoming image data and responds to changes in images. It adapts the functional block settings to correct for shifts in environmental conditions such as light level and illumination color temperature. The microcontroller will optimize these settings to provide the best quality image on all occasions.
4.1.3
Other functional blocks
Power management The hardware state of the STV0974 can be controlled by the power down pin (PDN). Upon the application of power to the STV0974 and PDN release, the STV0974 power-onreset cell issues a timed reset pulse and then releases the STV0974 into its boot state. The power-on-reset cell which output is the POR signal, is externally connected to the RST pin. Clocks In sleep mode, the STV0974 clock is derived from the clock signal applied to the CLK pin. In all other modes, the STV0974 clock is derived from the high speed clock received from the sensor.
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Functional description
STV0974
4.2
4.2.1
Sensor interface
Features

Low electromagnetic interference (EMI) interface with CMOS image sensors High speed serial receiver, with data and clock inputs Up to 120 Mbit/s operation using very low voltage differential signaling (vLVDS) VisionLink transfer protocol IC compliant master controller, 1.8 V interface, up to 400 kHz operation
4.2.2
Description
The STV0974 sensor interface is dedicated to the VS6552 image sensor that uses the VisionLink data transfer protocol over vLVDS. This includes:
An IC master controller supporting 1.8 V interface and 400 kHz operation. The IC master port signals are MSDA and MSCL that require external pull-up resistors. Internally, the IC master is a peripheral of the microprocessor control unit. Two vLVDS receivers for sensor data and clock signals, PDATA and PCLK differential pairs respectively. Each receiver accepts 1.8 V LVDS signals A VisionLink data synchronization and extraction unit, which extracts image timing references, active video and sensor status information. The extracted video stream in raw Bayer format along with active video strobes are connected to the video processing unit. The sensor status information is presented to the microprocessor control unit.
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STV0974
Functional description
4.3
4.3.1
Video processing unit
Features
Low-power dedicated hardware video processing unit, pipeline operation up to VGA resolution 30 Hz Image sensor correction stage including pixel defect correction and fixed pattern noise (FPN) cancellation Color interpolation stage with anti-aliasing and color matrix compensation Optical system compensation stage including anti vignetting and sharpness enhancement Noise reduction filter Programmable gamma and s-curve gamma for LCD support Full frame statistics gathering for exposure and color balance controls Programmable output image size (downscale by 1.5, 2, 2.5, 3, 4, 5 and 6)

4.3.2
Overview
Figure 2: Video processing unit
FPN
Color interpolation Color matrix To video processing unit and video compression unit
Anti-vignetting Input
Gamma Defect correction Scaler Noise reduction Sharpness enhancement
Statistics gathering
Microprocessor control unit
Fixed Pattern Noise (FPN) cancellation The FPN cancellation algorithm removes any column variability over the video area. Statistics gathering Image statistics are gathered on the full resolution input image and forwarded to the camera control unit for exposure and color balance control loops. Anti vignetting A radial gain is applied to the image luminance to compensate for possible luminance loss in the corners of the image due to an imperfect lens system. Defect correction The defect correction algorithm can detect and correct any defective pixels in a sensor array. Noise reduction filter The noise reduction filter is based on an adaptive algorithm. This algorithm performs filtering but does not affect image areas including significant information. Color interpolation Each pixel RGB components are calculated by interpolation of the incoming Bayer pattern.
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Functional description
STV0974
Color matrix Each pixel (RGB vector) is multiplied by a color matrix to adjust color balance. Viewfinder and live settings are independent to allow for optimization of both LCD display and capture for later viewing (i.e. on a PC). Sharpness enhancement A sharpening two-dimensional mask is applied to Green only and from interpolation. The resulting data is added (with a gain factor) to the matrix RGB data. Downscaler The downscaler unit extracts a rectangular region of interest and resizes the image by resampling video data. Standard image size such as CIF, QVGA and QCIF are available as well as a fully programmable custom size:
Table 3: Standard image size, VGA input Format
VGA CIF QVGA QCIF QQVGA SubQCIF QQCIF Custom
Image size
640 x 480 352 x 288 320 x 240 176 x 144 160 x 120 128 x 96 88 x 72 max VGA
Cropping
None 528 x 432 None 528 x 432 None None 528 x 432 Any
Scaling
None / 1.5 /2 /3 /4 /5 /6 Any
Comments
82.5% of input image used, centered
82.5% of input image used, centered
82.5% of input image used, centered See below
When custom size is selected, the crop and scale parameters are subject to the following constraints to ensure proper operation:

Output image size must be in 8 x 8 pixels increments Scaling factor can be any value giving an input image size within input limits
Gamma correction A non-linear gain is applied to each pixel's RGB components to compensate for the display's non-linearity. A standard curve is available for image capture for later viewing on a PC and an S-curve is available for LCD display. Coder The coder unit converts the internal RGB video stream to a user selectable output video format. It is based on a YUV digital video encoder with embedded synchronization codes, compliant with [1], extended with the support of RGB formats for viewfinder usage, as shown in Table 4.
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STV0974
Table 4: Output video formats Name
UYVY RGB565 RGB444
Functional description
Format
Y7Y6Y5Y4Y3Y2Y1Y0 U7U6U5U4U3U2U1U0 Y7Y6Y5Y4Y3Y2Y1Y0 V7V6V5V4V3V2V1V0 R4R3R2R1R0G5G4G3 G2G1G0B4B3B2B1B0 03020100R3R2R1R0 G3G2G1G0B3B2B1B0
Description
YUV (or YCBCR) 4:2:2 format as per [1] 16-bit RGB format for direct viewfinder on 64 K color LCDs. 16-bit RGB format for direct viewfinder on 4096 color LCDs. Uses 4 bit per RGB component, the four MSB's are zero padded. 8-bit RGB format for low bit rate viewfinder usage.
RGB332
R2R1R0G2G1G0B1B0
Byte ordering assumes a little endian memory system, i.e. in 16-bit formats, the least significant byte is sent first. For example, the UYVY format produces the sequence U Y0 V Y1... as per [1]. Note: Nevertheless various options are available to suit memory system requirements:

Byte ordering can be changed to big endian In YUV formats, the U and V components can be swapped In RGB formats, the R and B components can be swapped
YUV format processing The RGB pixel is converted to YUV coordinates according to ITU-R BT601 specification. The YUV coordinates are then rounded and clipped for an 8-bit representation. To produce a 4:2:2 digital component video, U and V components are filtered and down sampled by a factor of 2, coincident with Y sampling time. RGB format processing Dithering: In order to avoid contouring effects on low color depth displays, the RGB components are dithered prior to truncation to the required number of bits. Framing: The output frame is produced by performing the following steps: 1 Blanking code insertion: During video blanking intervals, blanking codes are inserted in the output stream. The default blanking code is the 16-bit pattern 0x1080, corresponding to Y = 0x10 and U/V = 0x80 as per [1]. 2 Synchronization pattern detection and correction: The coder performs detection of various synchronization patterns and applies a correction according to the current output format. 3 Video Timing Reference Code Insertion: A 4-byte sequence is inserted at the beginning and the end of each digital video line to delineate lines and frames in the video stream. The sequence is defined in [1] as FF 00 00 XY, where the XY byte is defined by:
Table 5: XY bits definition Bit
7 (msb) 6 5 4 3 2 1 0 (lsb)
Symbol
1 F V H P3 P2 P1 P0 Always 1.
Definition
Even / Odd Field. To maintain compatibility with[1], F is alternatively 0 or 1. V = 1 during field blanking, 0 otherwise. H = 1 during line blanking, 0 otherwise. Protection bit: P3 = V xor H Protection bit: P2 = F xor H Protection bit: P1 = V xor V Protection bit: P0 = F xor V xor H
SAV (Start of Active Video) is defined as the 4-byte sequence where H = 0. EAV (End of Active Video) is defined as the 4-byte sequence where H = 1.
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Functional description
STV0974
4.4
Video compression (VC)
Real time video compression permits a frame rate of 30 frame/s in any mode at VGA. The JPEG compression engine is a standard baseline sequential JPEG encoder [2]. The compression ratio can be modified by applying a multiplication factor on the quantization table. The quantization table can be scaled from a factor of 1/8 to a factor of 8. The STV0974 video compression block includes a baseline DCT JPEG encoder compliant with ISO DIS 10918-1. The JPEG encoder has the following characteristics:

baseline sequential DCT based encoder YUV 422 encoding only up to VGA image size scalable quantization table standard quantization table standard Huffman coder
The encoder top level block diagram is presented in Figure 3.
Figure 3: Encoder top level block diagram
Raster to block converter
Discrete Cosine transform
ZigZag transform Quantize
Entropy coder
The input data is a YUV 422 8-bit data stream in raster order. The output data is a baseline JPEG data stream.
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STV0974 4.4.1 Raster to block converter
Functional description
This block transforms the raster scan ordered data into block based ordered data. This data ordering is compliant with ISO DIS 10918-1 Annex A - Section A.2.
Figure 4: Data sequence at Raster to block input
pixel 1 line 1 Y Y Y Y Y Y Y Y U U U U U U U U Y Y Y Y Y Y Y Y V V V V V V V V Y Y Y Y Y Y Y Y U U U U U U U U Y Y Y Y Y Y Y Y V V V V V V V V Y Y Y Y Y Y Y Y U U U U U U U U Y Y Y Y Y Y Y Y V V V V V V V V Y Y Y Y Y Y Y Y U U U U U U U U Y Y Y Y Y Y Y Y V V V V V V V V Y Y Y Y Y Y Y Y U U U U U U U U pixel n Y Y Y Y Y Y Y Y V V V V V V V V
line m
Y Y Y Y Y Y
U U U U U U
Y Y Y Y Y Y
V V V V V V
Y Y Y Y Y Y
U U U U U U
Y Y Y Y Y Y
V V V V V V
Y Y Y Y Y Y
U U U U U U
Y Y Y Y Y Y
V V V V V V
Y Y Y Y Y Y
U U U U U U
Y Y Y Y Y Y
V V V V V V
Y Y Y Y Y Y
U U U U U U
Y Y Y Y Y Y
V V V V V V
The sequence of the input data stream is the following: line 1 from left to right up to pixel n, then line 2 from left to right......up to line m, pixel n. The output data stream sequence is block based. The image is segmented into MCU (minimum coded units) as illustrated in Figure 5.
Figure 5: MCU data order
pixel 1 line 1 16 pixels 8 pixels MCU(1,1) MCU(2,1) MCU (n/16 -1,1) MCU (n/16,1) pixel n
MCU(1,n/8) line n
MCU(2,n/8)
MCU(n/16 -1,n/8) MCU (n/16,n/8)
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Functional description
The MCU sequence order is top left to top right and top to bottom.
STV0974
Figure 6 shows the MCU structure made of 4 blocks: 2 blocks of 8x8 Y component, 1 block of 8x8 U component and one block of 8x8 V component. The series of blocks must be processed according to this order.
Figure 6: Structure of each MCU
MCU
Y BlockY1
Y BlockY2
U BlockU
V BlockV
Each block is composed of 8x8 components. Figure 7 presents the structure of BlockY1, as an example.
Figure 7: Structure of block Y1
BlockY1 YYYYYYYY YYYYYYYY YYYYYYYY 8 YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY 8
The data sequence inside each block is left to right and top to bottom. To summarize, at the output of Raster to Block converter, the data order is the following: Y data of blockY1 of first MCU (64 data from left to right, then top to bottom) Y data of blockY2 of first MCU (64 data from left to right, then top to bottom) U data of blockU of first MCU (64 data from left to right, then top to bottom) V data of blockV of first MCU (64 data from left to right, then top to bottom) Y data of blockY1 of second MCU (64 data from left to right, then top to bottom) Y data of blockY2 of second MCU (64 data from left to right, then top to bottom) U data of blockU of second MCU (64 data from left to right, then top to bottom) V data of blockV of second MCU (64 data from left to right, then top to bottom) ... up to last image MCU.
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STV0974 4.4.2 Discrete Cosine Transform
Functional description
This block performs a Discrete Cosine Transform on the incoming data stream. It is compliant with ISO DIS 10918-1 Annex A - Section A.3. The block processes each 8x8 input block to transform them into 8x8 DCT coefficients. The calculation of the DCT coefficients is done by the formula: 7 7
2 F ( u, v ) = --- x N
with
( 2x + 1 )u ( 2y + 1 )v C ( u )C ( v ) f ( x, y ) cos --------------------------- cos --------------------------16 16
x = 0y = 0
1 C ( u ) ,C ( v ) = -----2
u, v ) = 0 (
C ( u ) ,C ( v ) = 1
u, v ) 1/4 0 (
4.4.3
Zigzag transform
This block is in charge of setting the DCT coefficients in a sequence that corresponds to an increasing spacial frequency of the cosine function. It is compliant with ISO DIS 10918-1 Annex A Section A.3.6.
Figure 8: ZigZag block sequence re-ordering
12 3 4 5 6 7 8 1 3 2 5 6 7 15 16 28 29
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Input data sequence
8 14 17 27 30 43
4 9 13 18 26 31 42 44 10 12 19 25 32 41 45 54 11 20 24 33 40 46 53 55 21 23 34 39 47 52 56 61 22 35 38 48 51 57 60 62 36 37 49 50 58 59 63 64 Output data sequence
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Functional description 4.4.4 Quantization block
STV0974
This block applies a uniform quantizer on all DCT coefficients, in ZigZag sequence. It is compliant with ISO DIS 10918-1 Annex A - Section A.3.4. The quantizer step size for each DCT coefficient Suv is the value of the corresponding element Q'uv from the quantization table Q'.
Suv Squv = round ------------ Q'uv
Where uv is the index of the zigzag coefficient. Table Q' is a scaled quantization table calculated for table Q as follows:
Squeeze Q' = ------------------------- x Q 32
where Squeeze is a parameter value. Table Q is represented in Figure 9, as described in ISO DIS 10918-1 Annex K.
Figure 9: Luminance and chrominance quantization tables
16 12 14 Q = 14 18 24 49 72
11 12 13 17 22 35 64 92
10 14 16 22 37 55 78 95
16 19 24 29 56 64 87 98
24 26 40 51 68 81 103 112
40 58 57 87 109 104 121 100
51 60 69 80 103 113 120 103
61 55 56 62 77 92 101 99
17 18 24 Q = 47 99 99 99 99
18 21 26 66 99 99 99 99
24 26 56 99 99 99 99 99
47 66 99 99 99 99 99 99
99 99 99 99 99 99 99 99
99 99 99 99 99 99 99 99
99 99 99 99 99 99 99 99
99 99 99 99 99 99 99 99
Quantization table for Y blocks
Quantization table for U and V blocks
Table 6 shows an example of VGA image when different squeeze values are applied by the user.
Table 6: VGA image size - YUV 4: 2: 2 - Example of image size after JPEG compression
Squeeze Squeeze quantization table factor (Squeeze/8) File size (Kbyte) Bit per pixel 614
a
2 0.12
4 0.25
8 0.5
10 0.62
20 1.25
30 1.87
50 3.12
67 4.19
~80 2.13
~51 1.39
~32 0.85
~27 0.72
~21 0.56
~12 0.32
~9 0.24
~9 0.24
a. No compression
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STV0974 4.4.5 Entropy coder
This block performs the following functions:

Functional description
insertion of JPEG Markers runlength encoding Huffman encoding
4.4.5.1 JPEG markers These markers are compliant with ISO DIS 10918-1 Annex B. The output JPEG file includes markers defined in Table 7, in order of appearance.
Table 7: JPEG markers included in STV0974 output data stream Marker Function
Start of image Define Quantization Table Start of frame for baseline DCT Define Huffman Tables Start of Scan End of image SOI DQT SOF0 DHT SOS End of image
Name
FFD8 FFDB FFC0 FFC4 FFDA FFD9
Value
4.4.5.2 Runlength and Huffman encoding Encoding of DC coefficient The so-called DC coefficient is the first coefficient of each DCT data block. This DC coefficient is coded through its DPCM difference with its previous value, which is huffman encoded. This is described in ISO DIS 10918-1 Annex A - Section F.1.2.1. The DC Huffman tables are described in ISO DIS 10918-1 Annex A - Section K.3.
Figure 10: Encoding of DC coefficient
DCT coefficient numbers in zigzag order 1 12 DC 2 4 3 16 4 77 AC Block Y1 data values 63 1 64 0 1 4 DC 2 5 3 22 4 10 AC Block Y2 data values 63 0 64 0
In the example from Figure 10, the DC coefficient in Block Y2 is equal to 4, the previous Luminance DC coefficient is 12 (DC coefficient of Block Y1). The DPCM value is 4-12 = -8 and the encoded value will be Huffman (-8). The code that is generated is Code = DC Huffman (-8). Encoding of AC coefficients The 63 left coefficients of each DCT block are called AC coefficients. They are encoded using runlength and Huffman encoder. The run-length encoding consists in counting the number of zero values between each non-zero coefficient. When a non zero coefficient is found, the Huffman code of the pair (number of preceding zero, Number value) is Huffman encoded. If a run contains more than 15 zeros, a specific number called ZRL is Huffman encoded. If all the values up to the end of the block are equal to zero, a specific code called EOB is Huffman encoded.
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Functional description
The Huffman table used are described in ISO DIS 10918-1 Annex A - Section K.3.
Figure 11: Encoding of AC coefficient
1 12 DC 2 0 3 0 4 77 AC Block Y1 data values DCT coefficient numbers in zigzag order 63 64 1 2 3 1 0 4 DC 5 22 4 10 AC Block Y2 data values 63 0
STV0974
64 0
In the above example, the first AC coefficient of Block Y1 is 0, as good as the second one. The zeros are not Huffman encoded, but the runlength counts them. When the first non-zero value is reached (Coefficient 4 with value 77), the Huffman code for the pair (number of preceding zeros, value) = (2,77) if Huffman encoded. The code that is generated is Code = Huffman (2,77).
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STV0974
Functional description
4.5
4.5.1
Microprocessor interface
Features

8-bit microprocessor interface, asynchronous read/write, one address bit Indirect access to image sensor and coprocessor control registers Direct access to image data (JPEG compressed or uncompressed) On-chip 2048 byte image FIFO Interrupt request output 8/16/32-byte burst DMA support 2 Kbyte video FIFO for JPEG data and 10 Kbyte FIFO for non-JPEG data
4.5.2
Description
The STV0974 can be connected to any general purpose 8-bit microprocessor via the microprocessor interface. This interface substitutes functionally to the YUV and IC interfaces, i.e. both data and control flows are handled through the interface which provides:
access to the image data FIFO for fast transfers of scaled-down viewfinder images or fullresolution captured and compressed image data. For host systems with DMA support, a DMA request line is provided, as well as programmable FIFO threshold for burst operation. For other systems, an interrupt request output line is provided.The 2048-byte FIFO allows for greater host system latencies; to suit system requirements, the FIFO threshold is programmable. access to the camera subsystem configuration and control registers, through an address/data register pair and a status register for data polling. Access requests are posted to the internal controller core that handles the request (as in IC mode) and finally acknowledges through the microprocessor interface status register.
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Functional description 4.5.3 Direct registers
STV0974
Access to the microprocessor interface direct registers is controlled by the state of CSN, RDN, WRN and RS (Table 8).
Table 8: Microprocessor Interface Direct Registers CSN
0 0 0 0 1
RDN
1 0 1 0 X
WRN
0 1 0 1 X
RS
0 0 1 1 X Address Register (AR) Status Register (SR) Data Write register (DW) Data Read register (DR) No access
Register accessed
The direct registers are used to access all STV0974 indirect registers and external image sensor registers through IC. To read from a camera register: 1 Write AR with the indirect register address. 2 Poll the status register RDY bit until high. 3 Read the register data from DR. To write to a camera register: 1 Write AR with the indirect register address. 2 Write DW with the register data. 3 Poll the status register RDY bit until high.
Note: 1 16-bit values are in little-endian representation, i.e. LSB at lower address. 2 No data polling is required to access the microprocessor interface indirect registers.
Address Register (AR) The Address Register holds the 16-bit address of the camera register to access. AR is written by two consecutive byte writes, least significant byte first.
Note:
To avoid LSB/MSB sequence mismatch, any read access (to DR or SR) guarantees that the following write to AR updates the LSB (ADDR bits 7:0).
Table 9: Address Register Bits
15
Name
ME
Type
WO
Description
0 = Image sensor register (forward command to IC master). 1 = STV0974 register.
14
RW
WO
0 = Write access 1 = Read access
[13:0]
ADDR
WO
Camera register address.
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STV0974
Status Register (SR)
Functional description
The status register is an 8-bit read-only direct register holding all pending requests from the camera subsystem.
Table 10: Status Register Bits
7 6 5
Name
IRQ EOF
Type
RO -
Description
Interrupt Request: IRQ is set when at least one of the interrupt sources is set, and the corresponding bit mask is set. Reserved. End Of Frame: EOF is set by the falling edge of VENV (output image vertical envelope). SOF is cleared by writing ICLR bit 5.
4
SOF
RO
Start Of Frame: SOF is set by the rising edge of VENV (output image vertical envelope). SOF is cleared by writing ICLR bit 4.
3
MCI
RO
Micro-Core Interrupt: MCI is set by the micro-core to alert the host of the occurrence of an internal event (status update, error, etc....). MCI is cleared by writing ICLR bit 3.
2
FERR
RO
FIFO Error: FERR is set by the FIFO controller if a FIFO overflow occurs, or if the FIFO is not empty when cleared at the start of frame. FERR is cleared by writing ICLR bit 2.
1
FRDY
RO
FIFO Ready: This bit indicates that the number of valid bytes in the FIFO is greater than or equal to the FIFO threshold value, i.e: FRDY = (Nbytes threshold) During the inter-frame period, `threshold' is forced to `1' to flush the FIFO; otherwise, `threshold' is determined by FHTR. FRDY is level sensitive, i.e. it can be cleared only by reading FIFO.
0
RDY
RO
Ready: This bit indicates the state of the access request between the host and the STV0974: 0 = Register access in progress, 1 = AR, DR and DW can be accessed by the host. For a read access, RDY is cleared upon host write to AR (MSB); it is set by the microcore when DR is updated with the register data. For a write access, RDY is cleared upon host write to DW; it is set by the micro-core when the internal register is updated. Note: RDY is high when AR points to the interface indirect registers.
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Functional description
Data Write Register (DW)
STV0974
The data write register contains the byte to transfer to a camera register. DW can be written only when SR bit RDY is set.
Table 11: Data write register Bits
[7:0]
Name
DW
Type
WO
Description
Data Byte to write to camera subsystem.
Data Read Register (DR) The Data Read Register contains the byte transferred from a camera register. DR is valid only when SR bit RDY is set.
Table 12: Data Read register Bits
[7:0]
Name
DR
Type
RO
Description
Data Byte read from the camera subsystem.
4.5.4
Indirect registers
The microprocessor interface indirect registers are accessed by the host using an indirect address base of 0x8FF0 / 0xCFF0 (write / read). Register offsets are listed in Table 13:
Table 13: Microprocessor interface indirect register map a b Offset
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
Name
FIFO MICR IMASK ICLR FTHR FCNT FIFO read register.
Description
Microprocessor interface control register Interrupt mask register Interrupt clear register FIFO threshold register. FIFO count register.
a. 16-bit values are in little-endian representation, i.e. LSB at lower address. b. No data polling is required to access the microprocessor interface indirect registers.
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STV0974
FIFO Register (FIFO)
Functional description
FIFO is a read-only register. When read, FIFO returns the least recent byte from the image data FIFO, decrements the byte count and releases the FIFO interrupt if the count is lower than the threshold. Reading from an empty FIFO returns the last valid byte read. The image data FIFO is cleared at the beginning of VENV, the image vertical envelope. If the FIFO is not empty, its contents are discarded and the FERR flag is raised in the status register SR. New image data start to fill in the FIFO. If an overflow occurs during VENV, the FERR flag is also raised in SR; FERR can be cleared through ICLR.
Table 14: FIFO register Bits
[7:0]
Name
FIFO
Type
RO
Description
Image data byte (uncompressed or compressed).
Microprocessor Interface Control Register (MICR) MICR controls and configures the image data transfer.
Table 15: Microprocessor Interface Control Register Bits
[7:6] 5 IRQPOL
Name
-
Type
Reserved. IRQ pin polarity: 0 = active high 1 = active low
Description
RW
4
DRQPOL
RW
DRQ pin polarity: 0 = active high 1 = active low
[3:2]
BSIZE
RW
DMA burst size and enable: 00 = DMA operation disabled, DRQ pin is high impedance 01 = 8-byte burst 10 = 16-byte burst 11 = 32-byte burst
1 0
CLR
WO
Reserved, read as zero, ignored upon write Clear FIFO (Write Only, read as 0): 0 = No action 1 = Reset FIFO to empty state
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Functional description
Interrupt Mask Register (IMASK)
Table 16: Interrupt Mask Register Bits
[7:6] [5:0]
STV0974
Name
IMASK -
Type
Reserved
Description
RW
Each IMASK bit set to `1' enables the corresponding interrupt source bit in the status register (SR)
Interrupt Clear Register (ICLR)
Table 17: Interrupt Clear Register Bits
[7:6] [5:2] [1:0]
Name
ICLR -
Type
WO Reserved
Description
Each ICLR bit written with a `1' clears the corresponding interrupt source bit in the status register (SR). Writing a `0' has no effect Reserved
FIFO Threshold Register (FTHR)
Table 18: FIFO threshold register Description FTRH NE = 1 NE = 0 Holds the FIFO threshold value threshold = 1 threshold = TH * 16 (TH is ignored) (TH valid range is [1, 2...127])
This register is used to program values such as 1 (flush), 16 or 32 (DMA burst) or any greater value up to 2032 for interrupt driven data transfer. Note that for proper DMA operation, `threshold' must be greater than or equal to the DMA burst size (MICR[BSIZE]).
Table 19: FIFO Threshold Register Bits
[15:11] [10:4] [3:1] 0
Name
TH NE -
Type
Reserved
Description
RW RW
Threshold value in 16-byte increments. Reserved Not Empty: 1 = Force threshold to 1 (TH is ignored) 0 = Normal
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STV0974
FIFO Count Register (FCNT)
Functional description
FCNT is a read-only 16-bit register, returning the current number of bytes available in the FIFO.
Table 20: FIFO Count Register Bits
[15:0]
Name
FCNT
Type
RO
Description
Number of bytes available in the image data FIFO.
4.5.5
Image transfer operation
Interrupt controlled transfer The STV0974 generates interrupts by asserting the IRQ signal. The host interrupt handler performs the following operations: 1 Read the status register SR to determine if the STV0974 is the interrupting device (IRQ bit) and detect the active interrupt sources. 2 Acknowledge pending interrupts by writing ICLR. 3 Service the interrupt source(s), i.e. for example: MCI: read micro-core status and error registers (camera control channel). SOF: trigger frame synchronous task. FF: empty the FIFO by reading 16-byte blocks (camera image data channel). RDY: read DR for a pending read, write next AR (low-level byte transfer). 4 Interrupts can be disabled through IMASK. DMA controlled transfer The STV0974 supports DMA operation for image data transfer: the DRQ output signal is used to trigger a DMA burst read transfer from peripheral to memory. A full image transfer under DMA executes as follows:
Figure 12: Full image transfer under DMA
Frame
FIFO level threshold
DRQ (POL = 0)
FIFO Read IRQ
1 2
1
n
1
n
1 The STV0974 is initialized: DMA burst size, FIFO is cleared. 2 DRQ is asserted when the image FIFO threshold is reached or exceeded. 3 The DMA controller starts performing the burst read transfer consisting of 8, 16 or 32 byte reads.
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Functional description
4 DRQ is released after the first byte is read.
STV0974
5 After the last byte of the burst is read, the transfer terminates on step 6 if the FIFO is empty and the frame end is reached. Otherwise, transfer continues on step 2. 6 IRQ is asserted to signal the end of image transfer; the DMA channel is closed and re-initialized for the next transfer. This behavior ensures that no request can be missed by the controller, assuming DRQ is an edgesensitive signal. DRQ polarity can be reversed through MICR[POL] bit.
Note: 1 During DMA transfer, it is assumed that reading DR returns a byte from the FIFO, which means that AR shall be pointing to the FIFO when the DMA channel is active. To access other registers while performing DMA, the DMA controller must be halted and pending transfers properly flushed; then indirect accesses to the camera subsystem can occur. Finally, AR must be restored and the DMA controller released. 2 At the end of the transfer, FIFO underrun can occur if the image size is not an integer multiple of the burst size: dummy bytes are appended at the end of the image buffer. Nevertheless, the JPEG endof-frame marker (0xffd9) delineates the buffer.
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STV0974
Functional description
4.6
4.6.1
Video output interface
Video synchronization
The STV0974 supports two modes of data stream synchronization. Either the data stream can be synchronized by separate HSYNC and VSYNC signal (see Section 4.6.3) or by Synchronization codes in the data stream (see Section 4.6.2).
4.6.2
Synchronization codes
Horizontal synchronization The horizontal synchronization signal can be embedded within the data. Figure 13 represents the synchronization codes generated in a line.
Figure 13: Embedded code horizontal timing
START OF DIGITAL LINE START OF DIGITAL ACTIVE LINE NEXT LINE
EAV Code F00X81 F00Y00 4
LINE BLANKING 8181 0000 81 00
SAV Code F00XDDDDDDDD F00Y01230123 4 4-data packet
EAV Code DDF00X 23F00Y
Vertical synchronization
Figure 14: Embedded codes in vertical timing
START OF DIGITAL FRAME
END OF DIGITAL FRAME
EAV Code 8181 0000 8181 0000
FRAME BLANKING 1 0 8181 0000
SAV Code F00X8181 F00Y0000 8181 0000
F00X818 F00Y000
Note:
The horizontal synchronization is not sent during vertical blanking.
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Functional description 4.6.3 HSYNC and VSYNC video synchronization
HSYNC and VSYNC synchronization timing is shown in the Figure 15.
Figure 15: Horizontal and vertical synchronization
HSYNC VSYNC Active EAV BlankingSAV H=1 H=0
STV0974
V=0
Active lines
V=1
Blanking
4.6.4
Data timing
The YUV timing and the 3 RGB timings are also represented on Figure 16, with the associated qualifying HCLK clock.
Figure 16: Timings with associated qualifying clocks
Data[7:0] YCbCr HCLK RGB565 RGB444 Data[7:0] Pix0_lsb Pix0_msb Pix2_lsb Pix2_msb Pix3_lsb Un,n+1 Yn Vn,n+1 Yn+1 Un+2,n+3
HCLK Pix0 Pix1 Pix2
Data[7:0] RGB332 HCLK
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STV0974 4.6.5 JPEG data on 8-bit parallel with qualification clock
Functional description
This interface outputs JPEG on parallel 8-bit IOs. Different synchronization can be provided, as described in Figure 17. There are no defined lines in a JPEG data stream. The whole stream is output as a single frame line with VSYNC and HSYNC asserted together. Polarities of HSYNC, VSYNC and HCLK are programmable.
Figure 17: JPEG data output
JPEG 8-bit data HSYNC VSYNC Data0 Data1 no data Data2 no data no data Data3
HCLKx2
HCLKx2
Extra bytes can be added at the end of the image to ease the host DMA task.
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Functional description
STV0974
4.7
Power management unit
The STV0974 is reset via the internal PowerOnReset cell (POR) or via an external control reset line. The device reset is controlled by the RST pin. The POR cell generates an output signal on the POR pin every time that the device external supply is switched off or the PDN pin is activated.
Figure 18: Reset of STV0974
Application with external reset line POR STV0974 (left unconnected) STV0974 Connection on application board Application with POR reset cell POR
RST Host control line
RST
The STV0974 enters into power-up phase in two circumstances:

when the supplies are turned on with PDN pin high. when the STV0974 exits from power-down (PDN pin rises with supplies already on).
At power-up, the STV0974 performs its initialization phase and goes into sleep mode.
Figure 19: State machine at power-up
Supplies turned on & PDN low Supplies Off Vdd = 0 Supplies turned-off Supplies PDN high turned-on & PDN high
Power-down
Supplies turned-off
PDN low
Boot
1
Sleep mode
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STV0974
Figure 20: Boot-up phase machine
Functional description
VDD
t1 t2 t3 t5
PDN RST POR Clk Mode
t4
Reset
Boot
Sleep
Timing constraints:
Table 21: Timing constraints Min. Max. Unit
t1 t2 t3 t4 t5
0 20 20 2 7
ms s clk cycles ms s
Note:
To be compatible with external power-on/internal power-down modes (ex: external VDD on and PDN low), all input pads from baseband side as well as SCL and SDA pads on both sensor and baseband sides are "fail-safe".
The "timing constraints" mentioned above correspond to the minimum delay needed between signals, in order to follow a correct power up sequence and insure an adequate initialization phase. Referring to the application schematics (Section 8), STMicroelectronics recommends to connect POR pin (internal supply) to RST pin (Reset).
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Functional description
STV0974
4.8
Clock input
This block generates all the necessary internal clocks from an input range defined in Table 22. The input clock pad accepts up to 26 MHz signals.
Table 22: System input clock frequency range System clock frequencya Min. (MHz)
6.5
Max. (MHz)
26
a. Standard supported input frequencies (in MHz): 6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2, 19.44, 26
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STV0974
Functional description
4.9
4.9.1
Camera control unit
Features

User mode transition I2C register map including high-level registers and low-level registers dedicated to scaler control
4.9.2
Description
Figure 21: State machine user mode transitions
VDD Power down Reset
PDN Boot
1 Sleep
Idle
Sleep 1 Idle Flash Capture Flash
Live Sleep Idle
Sleep Capture Capture
Sleep
Idle Viewfinder Live Idle
Viewfinder Live PDN: Power Down pin Viewfinder
Viewfinder Capture
i. the "1" transition is automatic ii. Flash mode requires a firmware patch. Contact ST support. iii. Flash mode is not available with the microprocessor interface
Modes
Power down Supply is internally cut. Reset. Transitional state Boot Sleep mode This mode ensures that the coprocessor consumes the lowest possible power and I2C control is possible. Patching should occur in sleep mode followed by setting the system clock parameters. Idle Mode The clock coming from the sensor is active and I2C control is possible. Viewfinder Mode The viewfinder mode can be used to display dithered images on low color depth local LCD displays. The programmable gamma allows for a wide range of displays. Different image sizes and data formats can be chosen.
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Functional description
STV0974
Still Mode This mode is used to take still pictures. Still picture parameters can be set for both image size and data format. the first image output has a guaranteed exposure and color balance. the number of frames output can also be set. Live Mode Live clips can be generated in all the data and image formats. Flash Mode Flash mode is used to take a single still picture and synchronously activate a flash gun signal and illuminate the scene during the exposure period of the pixels. Torch Mode For systems without a flash gun, a torch mode can replace the flash mode. Torch mode is a setting (rather than a mode) which supports illumination of devices by producing a longer illumination pulse with a lower intensity. In torch mode, illumination is switched on before the camera is operated in one of the standard operating modes: ViewFinder, still capture or live.
Mode transitions
Boot to sleep The microcore starts following PDN de-activation. The right configuration is obtained according to the following procedure: 1 Determine the sensor I2C chip address. 2 Read all sensor registers, either through I2C reads or status line interpretation. 3 Initialize internal registers. The device then automatically goes into sleep mode Sleep to idle When exiting sleep mode, the external clock register of the sensor is set, and the sensor goes into Idle mode.
Figure 22: Sleep to idle timing
t0 t1 t2
SCL/SDA 974 Mode MSCL/MSDA Sensor Mode CLK from sensor
Goto VF or Goto Live Sleep Idle
Go to clk Set external clock active Sleep
Get sensor Go to Idle characteristics Clock Active Clock Active
Idle
t0: Time to interpret Mode change command (< 1ms) t1: Time to set clk characteristics (< 1ms) t2: Time to get sensor characteristics (< 3ms) to go to idle
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STV0974
Functional description
Idle to viewfinder / live The sensor field and line lengths are set according to user-defined frame rate and data output format. The STV0974 processes all sensor data on the fly. Exposure and white balance controls are computed at the end of each frame.
Figure 23: Idle to viewfinder or live
SCL/SDA
Goto VF or Goto Live
974 Mode MSCL/MSDA
Idle
VF or Live
Sensor settings
Goto Video Active Video Active
Sensor Mode VisionLink data
t0
Idle
t1
t2
t3
t0: Time to interpret Mode change command (< 1ms) t1: Time to set VF or Live parameters inside the STV0974 and to send VF or Live settings to the sensor (~2ms) t2: Time to go from Idle to Video Active state (Sensor side) t3: Exposure time (Sensor side). It depends on the frame rate.
Viewfinder / live to idle The STV0974 processes all the frame data and switches to idle mode after the last byte. See Figure 24 below.
Figure 24: Viewfinder or live to idle timing
SCL/SDA 974 Mode STV0974 output data MSCL/MSDA Sensor Mode VisionLink data
Goto Idle VF or Live Idle
Goto Idle Video Active Idle
t0
t1
t2
t0: Time to interpret Mode change command (< 1ms) t1: Time to finish sending frame (< 33 ms) t2: Time to flush all the STV0974 video pipe and the interface FIFO (interface dependant)
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Functional description
STV0974
Viewfinder to live/ Live to viewfinder The sensor field and frame lengths are set according to the user defined Live/Capture frame rate and data output format. The latency of this transition is minimal. See Figure 25 below.
Figure 25: Viewfinder to live or live to viewfinder
SCL/SDA
Goto other streaming mode VF or Live Live/VF
974 Mode MSCL/MSDA Sensor Mode STV0974 output data
Video Active
1 frame max.
2 frames max.
Idle to capture Data is grabbed as fast as possible for exposure and white balance convergence. When the system is stable (or timed-out), the user settings are sent to the sensor. See Figure 26.
Figure 26: Idle to capture timing
SCL/SDA 974 mode Output link MSCL/MSDA
capture Idle Capture in progress Capture
Sensor mode Input link
Idle
Video active
3 ms max.
Max = 20 frames @ maximum frame rate max 2 frames Mean ~8 frames Min. = 1 frame
Viewfinder to capture Two cases can occur: 1 The system (exposure, white balance) is already stable in viewfinder mode. The user settings are sent to the sensor. The processed frame is sent after a short latency. 2 The system has not stabilized. STV0974 enters transient mode and, when stable, automatically goes into Capture mode.
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STV0974
Functional description
Once the image is sent, the STV0974 automatically returns to Idle. See Figure 27.
Figure 27: Viewfinder to capture timing
SCL/SDA 974 mode STV0974 output data
capture ViewFinder Capture in progress Capture
MSCL/MSDA
Sensor mode
Video active
VisionLink data
Max 1 frame Max 20 frames(Note 1) Min = 0 frame Max 2 frames
Note:
1 If the system exposure and white balance is already stable, the maximum delay is 1 frame.
Idle to Flash In idle mode, white balance must be set to a fixed setting (automatic white balance setting is not recommended as no convergence is applied) and the "delay transfer mode" must be set to 0 (no frame delay). When changing to flash mode, the maximum frame rate is automatically set with respect to data format. The first frame is captured, processed and transferred by the STV0974. The system automatically goes back to idle mode. Figure 28 illustrates the timing in flash mode. When setting the torch mode, the flash mode should not be used. All the standard operating modes like ViewFinder, still capture or live operate normally. As an example, the automatic white balance and exposure control as well as "delay transfer mode" can be active if required.
Figure 28: Flash mode diagram
1
Exposure time
Sensor data output Strobe request from host Flash Strobe pulse (DIO12 pin) STV0974 data out 1 Exposure time of pixels is automatically set to maximum exposure time 2 Strobe pulse width is clipped to a maximum of 8 lines 2
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Functional description 4.9.3 IC register map
Register interpreter The STV0974 IC address is 0x08. The addressing space is defined in Table 23 and Table 24.
Table 23: Fields of address map Index Bit
15 14 13 [12-8] [7-0] bit15 = 0: reserved for the sensor bit15 = 1: STV0974 Pre-fetch read value 0: low-level register 1: high-level register Page group Register index
STV0974
Description
The customer accessible register map is divided into groups as listed in Table 24.
Table 24: Register groups Group
Register group [0] - System clock setup - High level operating modes - Output format control Register group [1] - Frame rate control - Image sizes - Stills capture setup Register group [2] - Image appearance setup - Image manipulation - JPEG control Register group [3] - Color saturation - Gamma control Register group [4] Register group [5] Register group [6] - Exposure control setup - White balance control - Flash mode management
Description
- System read only registers (e.g. sensor ID, firmware revision)
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STV0974
Functional description
There are restrictions related to the states at which registers can be accessed. Table 25 lists the state coding used in the register description.
Table 25: Register state coding State code
I V C L S A
Description
Registers can be accessed safely while the system is in idle state Registers can be accessed safely while the system is in ViewFinder state Registers can be accessed safely while the system is in capture mode state Registers can be accessed safely while the system is in live mode state Registers can be accessed safely while the system is in sleep mode state Registers can be accessed in all stable states
Register contents represent different data types as described in Table 26.
Table 26: Type of data State Code
I M B C
Description
Integer parameter. May be anywhere between 1 bit and 8 bit wide Multiple field registers Bit field register Coded register
Registers listed as reserved or read-only should NOT be written to, as this may cause unpredictable results. The data format for each register uses the following coding:

D = Data (1 or 0 as required) 0 = Data bit must be set to 0 1 = Data bit must be set to 1 X = Don't care (either 0 or 1 can be written with no system consequences) R = Reserved
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Functional description
4.9.3.1 High-level interface Register group 0
Table 27: System and status [register group 0] Name
Sensor ID Code MSB Sensor ID Code LSB Firmware Rom Version External Clock Frequency MSBa External Clock Frequency LSB 0xA005 R/W S MI
STV0974
Index
0xA000
R/W
R
State code
A
Data type
I
Format default
DDDD.DDDD
Description
0010.0010
0xA001 R A I DDDD.DDDD
Bit[15:4]: sensor type Bit [3:0]: Sensor revision
1000.XXXX
0xA002 R A I DDDD.DDDD Firmware version identifier
0001.0100
0xA004 R/W S MI RRDD.DDDD
1101.0000
RRDD.DDDD
External clock frequency in MHz coded as fixed point (5:11): Bit [15:11]: Integer part Bit [10:0]: Decimal part (1 unit = 1/ 2048 MHz) i.e. default value is 26MHz.
0000.0000
Sensor Clock Derating Mode Status
0xA006
R
S
I
RRRR.DDDD
Sensor clock deratingb [15-0]: Reserved [15]: Booting [14-7]: Reserved [6]: Flash [5]: Capture in progress [4]: Live [3]: Capture [2]: Viewfinder [1]: Idle [0]: Sleep
0000.0001
0xA007 R A I RRRR.DDDD
Mode Control
0xA008
R/W
A
I
RRRR.DDDD
[15-7]: Reserved [6]: Flash [5]: Reserved [4]: Live [3]: Capture [2]: Viewfinder [1]: Idle [0]: Sleep
0000.0000
Status Register
0xA009
R
A
I
DDDD.DDDD
STV0974 status (Table 10)
0000.0000
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STV0974
Table 27: System and status [register group 0] Name
Input / Output Protocol Control
Functional description
Index
0xA00A
R/W
R/W
State code
S
Data type
I
Format default
RDDD.RDDD
Description
Bit [7]: Reserved Bit [6:4]: Input 0: Reserved 1: VisionLink 2-3: Reserved 4: Color bars generator Bit [3]: Reserved Bit [2:0]: Output 0: Reserved 1: Reserved 2: I2C/ITU-R 656 embedded synchro 3: I2C /ITU-R 656 external synchro I2C / JPEG parallel output 4: Microprocessor interface controller / microprocessor interface 5: Reserved
0001.0100
a. See Clock input section, for standard external clock frequencies supported. b. The product limitation in derating mode is : 2: Half Speed -> Max I2C clock is 200 kHz 4: Quarter Speed -> Max I2C clock is 100 kHz
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Functional description
Register group 1
Table 28: Image characteristics [Register group 1] Name
Still and Live Sensor Frame Ratea
STV0974
Index
0xA100
R/W
R/W
State code
SIV
Data type
I
Format default
DDDD.DDDD
Description
Frame rate coded as fixpoint (6:2): Bit [7:2]: Integer part Bit [1:0]: Decimal part (1 unit = 0.25 frame/s) Default is 15 frame/s
0011.1100
Still and Live Output Image Size
0xA101
R/W
A
I
RRRR.RDDD
[7]: Custom b [6]: QQCIF [5]: SubQCIF [4]: QQVGA [3]: QCIF [2]: QVGA [1]: CIF [0]: VGA
0000.0000
Still and Live Output Image Format
0xA102
R/W
SIV
I
RRRR.RDDD
[4]: JPEG [3]: YUV 4:2:2 [2]: RGB 5:6:5 [1]: RGB 4:4:4 [0]: RGB 3:3:2
0000.0100
Still Multi-frames Transfer Mode Delay transfer Mode
0xA103
R/W
SIVL
B
DDDD.DDDD
0... 254: 0...254 frame(s) 255: continuous. 0... 254: Minimum number of frames (at 30 frame/s) to wait for before sending the requested still one. 255: Reserved
0000.0001
0xA104 R/W SI B DDDD.DDDD
0000.0000
Viewfinder Frame Rate (STV0974 input)a
0xA105
R/W
SILC
I
DDDD.DDDD
Frame rate coded as fix point (6:2)a: bit [7:2]: Integer part bit [1:0]: Decimal part (1 unit = 0.25 frame/s) Default is 15 frame/s
0011.1100
Viewfinder Image Size
0xA106
R/W
A
I
RRRR.RDDD
[7]: Customb [6]: QQCIF [5]: SubQCIF [4]: QQVGA [3]: QCIF [2]: QVGA [1]: CIF [0]: VGA
0000.0101
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STV0974
Table 28: Image characteristics [Register group 1] Name
Viewfinder Image Format
Functional description
Index
0xC107
R/W
R/W
State code
SILC
Data type
I
Format default
RRRR.RDDD [4]: JPEG
Description
0000.0011
[3]: YUV 4:2:2 [2]: RGB 5:6:5 [1]: RGB 4:4:4 [0]: RGB 3:3:2
a. The corresponding frame rates are considered as targets. If the target cannot be achieved due to derated sensor clock or output format versus output protocol, the closest possible frame rate is achieved, knowing that 30 frame/s is the highest frame rate supported by the device. b. For custom output sizes, please refer to Section 4.6. When continuous mode is selected (255), the grabbed image is output until the mode control register is modified.
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Functional description
Register group 2
Table 29: Image control [register group 2] Name
Antivignetting Correction
STV0974
Index
0xA200
R/W
R/W
State code
A
Data type
I
Format default
RRRR.DDDD
Description
Correction in tens of percentage 0: 0% 10: 100%, >10: Frozen
0000.0110
DEFCOR control
0xA201
R/W
A
M
DXXX.XXXX XDXX.XXXX XXDX.XXXX XXXD.DXXX
Bit[7]: Defect correction matrix (default is square matrix) Bit(6]: Defect correction enable (correction of bad pixels) Bit[5]: Defect scythe enable (Smooth filtering of good pixels) Bit[4:3]: Defect scythe rank (default is 0, maximum value means narrow filter) Bit[2:0]: Defect scythe weight (default is 7, maximum value means minimum weight applied) Nora control register. [0]: Nora disabled [7]: Nora max strength Default is 2
XXXX.XDDD
1010.0111
NORA control 0xA202 R/W A I RRRR.RDDD
0001.0010
Mirror
0xA203
R/W
SI
B
RRRR.RRXD RRRR.RRDX
Horizontal mirror Vertical mirror
0000.0000
Sharpness Gain 0xA204 R/W A I 00DD.DDDD Sharpness gain
0000.1100
Sharpness Enable JPEG Control 0xA205 R/W A B RRRR.RRRD
1111.1101
0xA206 R/W A I RDDD.DDDD
Sharpness enable Bit[7:2]: low peak Bit[1:0]: reserved Bit [7]: JPEG control 0: Automatic file size computation 1: Manual squeeze control Bit [6:0]: Control settings if bit[7] = 0: Requested size of final JPEG file (in Kbyte) if bit [7] = 1: Manual squeeze control with quantization table scaled by bit [6:0]/8. Applicable range of values for bit [6:0] is [2; 67]
0011.1110
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STV0974
Register group 3
Table 30: Color management [register group 3] Name
Still / live Gamma Standard Gain Still / live Gamma S-Curve gain
Functional description
Index
0xA300
R/W
R/W
State code
A
Data type
I
Format default
RRRR.DDDD
Description
Bit[3:0]: gain for standard Gamma curve Bit[3:0]: Gain for low S-curve part Bit[7:4]: Gain for high S-curve part
0000.0011
0xA301 R/W A M XXXX.DDDD DDDD.XXXX
0100.0100
Still / live Gamma Misc. 0xA302 R/W A M XRRR.DDDD DRRR.XXXX Bit[3:0]: S-curve pedestal bit [7] = 1 Standard Gamma bit[7] = 0 S-curve Gamma Bit[3-0]: Gain for standard Gamma curve Bit[3-0]: Gain for low S-Curve part Bit[7-4]: Gain for high S-Curve part
1000.0000
Viewfinder Gamma Standard Gain Viewfinder Gamma S-Curve gain Viewfinder Gamma Misc. 0xA303 R/W A M RRRR.DDDD
0000.0100
0xA304 R/W A M XXXX.DDDD DDDD.XXXX
0100.0100
0xA305 R/W A M XRRR.DDDD DRRR.XXXX Bit[3:0]: S-curve pedestal bit [7] = 1 Standard Gamma bit [7] = 0 S-curve Gamma Y range value (contrast enhancement) Bit[7:4]: Ceiling value
1000.0000
YCbCr Control Y range YCbCr Control Y ceiling YCbCr Control Y floor YCbCr Control CbCr saturationa 0xA306 R/W A I DDDD.DDDD
1000.0000
0xA307 R/W A M DDDD.XXXX
0001.0000
0xA308 R/W A M DDDD.XXXX
0000.0000
0xA309 R/W A I DDDD.DDDD
Bit[3:0]: Floor value (signed value in 2's complement) CbCr saturation
1000.0000
a. The maximum register value allowed is 144. For higher saturation capabilities, contact ST support.
Note:
YCbCr control registers are common for still/live and ViewFinder modes. As a consequence, if different settings are applied in these modes and if for example still capture is requested from ViewFinder mode, it is recommended to set a "transfer mode delay" corresponding to 1 frame minimum, and also to respect a minimum wait of half of a frame prior to changing the YCbCr settings.
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Functional description
Register group 4
Table 31: Exposure management [Register group 4] Name
AC Frequency
STV0974
Index
0xA400
R/W
R/W
State code
SI
Data type
B
Format default
DDDD.DDDD
Description
AC Frequency in Hz
0011.0010
Exposure weighting 0xA401 R/W A I RRRR.RRDD
0000.0000
Zone weight: [3]: Reserved [2]: Backlit [1]: Centered [0]: Flat One unit of compensation is equivalent to 1/3 EV. Default value is equivalent to 0 EV. [Default - 2] is equivalent to -2/3 EV. Valid range is 0 to 36
Exposure compensation
0xA402
R/W
A
I
DDDD.DDDD
0001.1001
Register Group 5
Table 32: White balance management [register group 5] Name
White Balance Mode
Index
0xA500
R/W
R/W
State code
A
Data type
I
Format default
RRRR.DDDD
Description
[15-9]: Reserved [8]: Reserved [7]: Reserved [6]: Reserved [5]: Reserved [4]: User manual (using registers below) [3]: Reserved [2]: Reserved [1]: Automatic [0]: Off White balance user setting for the red channel gain. Contact ST for support.
0000.0001
Manual White Balance Red channel Manual White Balance Green channel Manual White Balance Blue channel
0xA501
R/W
A
C
DDDD.DDDD
0000.0000
0xA502 R/W A C DDDD.DDDD
0000.0000
0xA503 R/W A C DDDD.DDDD
White balance user setting for the green channel gain. Contact ST for support. White balance user setting for the blue channel gain. Contact ST for support.
0000.0000
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STV0974
Register Group 6
Table 33: Flash mode management [register group 6] Name
Torch polarity
Functional description
Index
0x8A43
R/W
R/W
State code
I
Data type
I
Format default
RRRR.RDDD
Description
Bit[2:0]=0: Torch output (pin DIO12) signal is low Bit[2:0]=7: Torch output (pin DIO12) signal is high
RRR.R000
Torch control
0x8A44
R/W
I
I
RDRR.RRRR
R1RR.RRRR
Bit[6]=0: Torch output (pin DIO12) pad enable. Bit[6]=1: Torch output (pin DIO12) pad in high impedance
Flash pulse polarity Flash pulse length
0x8A45
R/W
I
I
RDRR.RRRR
Bit[6]=0: Flash pulse active high. Bit[6]=1: Flash pulse active low. Bit[2:0]: line length - 1 Default is 0, corresponding to 1 video line (maximum pulse allowed is 8 video lines).
R0RR.RRRR
0x88D4 R/W I I RRRR.RDDD
0000.0000
Note:
Access to the bits mentioned here above is done through a read-modify-write sequence. As an example, when torch mode is set: - when in idle mode: set 0x8A44 bit[6] to 0 to enable the torch mode set 0x8A43 bit[2:0] to 7 to light the torch (if the torch is active high) - go into required Active mode (still/live or ViewFinder): set 0x8A43 bit[2:0] to 0 to extinguish the torch In the case of flash mode: - when in idle mode: set 0x8A45 bit[6] to 1 to set the flash pulse active low (default setting is flash pulse active high) set 0x88D4 bit[2:0] to 7 to set the flash pulse length to 8 video lines set 0xA104 bit [7:0] to 0 to set 0 transfer frame delay set 0xA500 bit[3:0] to 5 to set white balance to "daylight" fixed setting - go into flash mode: the system automatically goes back to Idle.
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Functional description
4.9.3.2 Low-level interface Scaler low-level control
STV0974
These registers are active only if either "Still and Live Output Image Size" or "Viewfinder Image Size" registers are set to "custom" size.
Table 34: Scaler low-level control Name
Source centre Xposition MSB Source centre Xposition LSB Source centre Yposition MSB Source centre Yposition LSB Viewfinder Dest. Image Width MSB Viewfinder Dest. Image Width LSB Viewfinder Dest. image height MSB Viewfinder Dest. image height LSB Viewfinder Scaling factor
Index
0x8060
R/W
R/W
State code
A
Data type
I
Format default
RRRR.RRDD
Description
X-coordinates of the centre of the source image window. Default is 322
0000.0001
0x8061 R/W A I DDDD.DDDD
0100.0010
0x8062 R A I RRRR.RRDD
0000.0000
0x8063 R A I DDDD.DDDD
Y-coordinates of centre of the source image window. Default is 242
1111.0000
0x8064 R/W A I RRRR.RRDD
0000.0000
0x8065 R/W A I DDDD.DRRR
Width of the destination image (after scaling) in viewfinder mode. The value must be a multiple of 8 pixels. Height of the destination image (after scaling) in viewfinder mode. This value must be a multiple of 8 pixels. Scaling factor in viewfinder mode: [0]: Reserved [1]: x1 [2]: x2 [3]: x3 [4]: x4 (default) [5]: x5 [6]: x6 [7]: x1.5 [8]: x2.5
1010.0000
0x8066 R/W A I RRRR.RRDD
0000.0000
0x8067 R/W A I DDDD.DRRR
0111.1000
0x8068 R/W A I RRRR.RDDD
0000.0100
Still/Live Dest. Image Width MSB Still/Live Dest. Image Width LSB
0x8069
R/W
A
I
RRRR.RRDD
0000.0010
0x806A R/W A I DDDD.D000
1000.0000
Width of the destination image (after scaling) in still / live mode. This value must be a multiple of: - 2 pixels in YUV output format - 16 pixels in JPEG output format Registers only used for Capture when in idle mode
Still/Live Dest. image height MSB Still/Live Dest. image height LSB
0x806B
R/W
A
I
RRRR.RRDD
0000.0001
0x806C R/W A I DDDD.D000
1110.0000
Height of the destination image (after scaling) in still / live mode. This value must be a multiple of 8 pixels. Registers only used for Capture when in idle mode
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STV0974
Table 34: Scaler low-level control Name
Still / Live Scaling factor
Functional description
Index
0x806D
R/W
R/W
State code
A
Data type
I
Format default
RRRR.RDDD
Description
Scaling factor in Still/Live: 0: Reserved 1: x1 (Default) 2: x2 3: x3 4: x4 5: x5 6: x6 7: x1.5 8: x2.5
0000.0001
Note:
If the scaling factor it too high and the cropped image size is bigger than the full source image, the scaling factor is automatically set to the closest possible high value.
MMS Downscale zoom This section contains an example of how the low level scalar registers can be used to implement a down scale `zoom' feature suitable for MMS applications. The example assumes that the desired output image size is 160 x 120 pixels. The choice of output image size will limit the number of scaling options available. In this example we are able to select scaling factors 1, 1.5, 2, 2.5, 3 and 4. The source image from which the scaled output images are derived is always the full VGA array, 640 x 480 pixels. If a smaller output image is chosen, 96 x 80 for example, then clearly the entire scaling factor range would be available. With reference to the example below (Figure 29), a scaling factor of 4 actually yields a `zoom' of 1. This implies that the full scene field of view is preserved within the output image but heavily scaled. To ensure that the smaller scaling factors produce the same output image size it is necessary for the video processor to crop the source VGA image prior to scaling. This has the effect of limiting the scene field of view but yields the `zoom' effect.
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Functional description
Figure 29: MMS crop zoom example
STV0974
VGA (640 x 480) source image scaled for use in this document Set of images below are crop/scales to 160x120 pixels for final display 1. Scale by 1 from 160x120 crop 2. Scale by 1.5 from 240x180 crop 3. Scale by 2 from 320x240 crop 4. Scale by 2.5 from 400x300 crop 5. Scale by 3 from 480x360 crop 6. Scale by 4 from 640x480 crop
1.
Zoom factor = 4
4.
Zoom factor = 1.6
2.
Zoom factor = 2.67
5.
Zoom factor = 1.333
3.
Zoom factor = 2
6.
Zoom factor = 1
4.9.3.3 Status error codes A read from the Status Register (0xA009) yields status error codes as described in the table below. The Status Register contents are reset to 0x00 by a write to the Mode Control register.
Table 35: Status error codes Error code value
0x00 0x21 0x22 0x23 0x41 No error Sensor communication problem Sensor temporarily not accessible. Retry. Incompatible sensor JPEG File too big Re-grab new image One of the requested JPEG frames is larger than the target. User to restart capture command Sensor not responding. Need to go back to Idle.
Description
Troubleshooting
0x51
Time out
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STV0974
4.9.3.4 Firmware patching
Functional description
The STV0974 has some firmware patching capabilities addressable through I2C and microprocessor interfaces through control registers firmware patch code downloads. Up to 15 different patches can be downloaded within a limit of 512 bytes of RAM.
Table 36 : Patch control registers Name
Patch enable
Index
0x84BF
R/W
W
Format default
RRRR.RRDD
Description
bit [1:0] = 01 patch enabled bit [7:2] = 10 patch disabled
Patch address
0x8480 Ox8481
W
RRRR.RRRR RRRR.RRRR
bit [15:0] = Reserved Patch address delivered by ST bit [15] = 1 bit [14:0] = Patch memory offset
Patch memory offset
0x84A0 0x84A1
W
1DDD.DDDD
DDDD.DDDD
The patch space starts from address 0x8600. Patch structure: "disable all patches" "set address to patch" "set offset of patch in memory" "write patch in memory (starting from address 0x8600 + patch memory offset)" "enable all patches" The state in which to download the patch depends on the nature of the patch, most likely either idle or sleep mode. Please contact ST support for patch delivery and recommendations for ideal use.
4.10
Additional features
There are a number of additional features which are supported by the STV0974, however implementation of these features is not supported by this datasheet. Please contact the ST support team for support of these features if you have a specific requirement.
The polarity of the HSYNC and VSYNC signal can be programmed. However, these are nonstandard settings. The transmitted byte order of the RGB and YUV is programmable. The viewfinder color matrix can be programmed to match the characteristics of a local LCD display.

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Electrical characteristics
STV0974
5
5.1
Electrical characteristics
Absolute maximum ratings
Symbol
VDD (including VCORE & VDDPOR) Voltage on any signal pin IDD Supply current Current on any signal pin TSTO TLEAD, 974E TLEAD, 974 Storage temperature Lead temperature (soldering, 10 s) for lead-free package Lead temperature (soldering, 10 s) for leaded package -0.5 to (VDD + 0.5) 100 10 -40 to 150 +260 +225 V mA mA C C C Supply voltage
Parameter
Value
-0.5 to +2.2
Unit
V
Caution: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
5.2
Operating conditions
Symbol
VDD TA Supply voltage Ambient temperature
Parameter
Value
+1.7 to +1.9 -25 to +70
Unit
V C
5.3
Thermal data
Symbol
Rth(j-a)
Parameter
Junction-ambient thermal resistance - TFBGA56a
Value
65
Unit
C/W
a. Typical, measured with the component mounted on an evaluation PC board in free air.
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STV0974
Electrical characteristics
5.4
DC electrical characteristics
Over operating conditions unless otherwise specified.
Symbol
VIL VIH VOL VOH IIL
Parameter
Input low voltage Input high voltage Output low voltage Output high voltage Input leakage current Input pins I/O pins Input capacitance SCL, MSCL Input / Output capacitance SDA, MSDA
Test conditions
Min.
-0.3 0.7 VDD
Max
0.3 VDD VDD + 0.3 0.2 VDD
Unit
V V V V
IOL < 2 mA -IOH < 2 mA VSS < VIN < VDD 0.8 VDD
10 1 6
A A pF pF
CIN CI/O
TA = 25 C, freq. = 1 MHz TA = 25 C, freq. = 1 MHz 8
Table 37: Power supply specificationsa Symbol
IDDPD IDDIDLE IDDACTIVE_ JPEG IDDACTIVE NON_JPEG
Parameter
VDD supply current in power-down mode VDD supply current in idle mode VDD supply current in active live mode VDD supply current in active live mode
Test Conditions
VDD = max ; PDN < VIL VDD = max ; mode = idle. VDD = max ; mode = live or ViewFinder or capture JPEG at VGA 30 frame/s. VDD = max ; mode = live or ViewFinder or capture YUV at VGA 30 frame/s.
Typ.
5 15 65
Max
20 25 75
Unit
A mA mA
55
75
mA
a. Same power consumption for Viewfinder, live and capture modes if same output image size and output data format.
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Electrical characteristics
STV0974
5.5
5.5.1
AC electrical characteristics
CLK
Table 38: CLK electrical characteristics (Figure 30) Symbol
VCDC fCLK
Parameter
DC coupled square wave voltage Clock frequency input
Min.
1.7 6.5
Typ.
1.8 13
Max.
1.9 26
Unit
Vp-p MHz
Figure 30: CLK electrical characteristics
1/fCLK VCDC
5.5.2
I2C slave timing
Table 39: I2C slave timing (Figure 31) Symbol
fSCL tLOW tHIGH tSP tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH SCL clock frequency Clock pulse width low Clock pulse width high Pulse width of spikes which are suppressed by the input filter Bus free time between transmissions Start hold time Start set-up time Data in hold time Data in set-up time SCL / SDA rise timea SCL / SDA fall timea Stop set-up time Data out hold-time 0.6 0 0.6 0.9 1.3 0.6 0.6 0.15 100 300 300 0.9 1.3 0.6 50
Parameter
Min.
Typ.
Max.
400
Unit
kHz s s ns s s s s ns ns ns s s
a. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum capacitance on both SDA and SCL.
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STV0974
Figure 31: I2C slave timing
Electrical characteristics
Stop
Start
Start
Stop
SDA tBUF SCL tLOW
tR
tF
tHD.STA
tHD.STA
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
Note:
tDH is the same timing as tHD.DAT. tDH is a value driven by the STV0974. tHD.DAT is the value when the host is driving.
5.5.3
I2C master timing
Table 40: I2C master timing Symbol
fSCL tLOW tHIGH tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH
Parameter
MSCL clock frequency a Clock pulse width low Clock pulse width high Bus free time between transmissions Start hold time Start set-up time Data in hold time Data in set-up time MSCL / MSDA rise time
b
Min.
Typ.
200
Max.
400
Unit
kHz s s s s s
1.1 0.6 1.3 0.6 0.6 0.15 100 300 300 0.6 0 0.6 0.9 0.9
s ns ns ns s s
MSCL / MSDA fall time b Stop set-up time Data out hold-time
a. 200 kHz recommended through system patch. Please contact ST for details. b. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum capacitance on both MSDA and MSCL.
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Electrical characteristics
Figure 32: I2C master timing
Stop Start Start
STV0974
Stop
SDA tBUF SCL
tLOW
tR
tF
tHD.STA
tHD.STA
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
i. tDH is the same timing as tHD.DAT. tDH is a value driven by the STV0974. tHD.DAT is the value when the host is driving.
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STV0974 5.5.4 Video output timing
Table 41: Video output timing (Figure 33) Symbol
tDS tDH tCKH tCKP tCKR
Electrical characteristics
Parameter
Data and synchro setup timea Data and synchro hold time a Clock pulse width high a Clock period a Clock rise timea
Min.
10 10 16
Typ.
Max.
Unit
ns ns ns
44 5
ns ns
a. with a 12 pF capacitance
Figure 33: Video output timing
tCKP tCKH
hclk tDS Data[7:0] hsync/vsync tDH
tCKR
5.5.5
Microprocessor read/write timing
Table 42: Microprocessor read and write cycle timingv Symbol
tAS tAH tRACC tLZ tRP tWP tWDS tRREC tWREC tZL tRDH tWDH
Parameter
RS, CSN valid to RDN or WRN low RS, CSN hold after RDN or WRN high Read access time RDN high to data high impedance Read pulse width Write pulse width Data setup to WRN high Read recovery time Write recovery time RDN low to data low impedance RDN low to data invalid Data hold after WRN high
Min.
7 7
Typ.
Max.
Unit
ns ns
40 15 40 45 35 30 22 0 0 5
ns ns ns ns ns ns ns ns ns ns
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Electrical characteristics
Figure 34: Read cycle timing
STV0974
RS CSN tAS tRP RDN (WRN high) tRACC tZL tRDH tAH tRREC tLZ
Data[7:0]
Figure 35: Write cycle timing
RS CSN tAS tWP WRN (RDN high) tAH tWREC tWDH
tWDS
Data[0:7]
5.5.6
VisionLink serial receiver timing
Table 43: VisionLink serial receiver input timing (Figure 36) Symbol
tDS tDH tCKP Data setup time Data hold time Clock period
Parameter
Min.
1 2.7 8.3
Typ.
Max.
Unit
ns ns ns
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STV0974
Figure 36: VisionLink basic input timing
tCKP PCLK
Electrical characteristics
tDS
tDH
PDATA
Table 44: Receiver VisionLink / SubLVDS electrical characteristics Symbol
VI VIDTH tPWRUP/ PWRDN
Parameter
Input common mode voltage range Input differential threshold (Va -Vaz) Power-up/-down time
Min
VDD /2 0.4 +/-50
Typ
VDD/2
Max
VDD/2 + 0.4 +/-200
Unit
V mV s
2
10
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Package mechanical data
STV0974
6
6.1
Package mechanical data
Pin assignment
Figure 37: STV0974 pin assignment
1 A
2
3
4
5
6
7
8
9
10
VSS DIO2 DIO1 DIO0 RST
POR VDD
B
VDD
VCORE VSS VDDPOR VSS
C D
NC NC
NC NC VSS PDATAP PDATAN VDD
TMS
VSS
TDI
TCK PDN TDO CLK MSCL MSDA
SCL SDA VSS VDD DIO8 DIO9 DIO10
E F G
VCORE PCLKP PCLKN
H J K
VSS DIO3
VSS VCORE VSS
VDD VCORE
DIO4 DIO5 VDD DIO6
DIO7 DIO13 DIO12 VSS DIO11 VDD
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STV0974
Package mechanical data
6.2
Package dimensions
Table 45: TFBGA 6x6x1.20 56 2R10 0.50 - Package dimensions a b c Reference
A A1 A2 b D D1 E E1 e F ddd .eee .fff e
d
Min.
1.010 0.150
Typ.
Max.
1.200
Unit
mm mm
0.820 0.250 5.850 0.300 6.000 4.500 5.850 6.000 4.500 0.500 0.600 0.750 0.900 0.080 0.15 0.05 6.150 0.350 6.150
mm mm mm mm mm mm mm mm mm mm mm
a. Max mounted height is 1.20mm. Based on a 0.27mm ball pad diameter. Solder paste is 0.15mm thickness and 0.27mm diameter. b. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array. Thin profile: -The total profile height (Dim A) is measured from the seating plane to the top component - A = (1.01 to 1.20) mm - Fine pitch: e>1.00mm pitch c. The terminal A1 corner must be identified on the top surface of the package by using a corner chamfer, ink or metallized markings, indentation or other feature of package body or integral heatslug. - A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. d. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. e. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.
.
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Package mechanical data
Figure 38: TFBGA 56 6x6x1.2 2R10 0.5
STV0974
seating plane
C
ddd
A2
A1
D A
A
D1 e F
B
K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10
F
0b (56 balls)
A1 corner index area (see note 3)
bottom view
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e
E1
C
STV0974
PCB layout guide lines for the STV0974 and VS6552
7
PCB layout guide lines for the STV0974 and VS6552
Normal good PCB design practice should be observed for the layout of the STV0974. Power and ground planes should be used to supply power to STV0974. The high speed subLVDS signal pairs (PCLKP,PCLKN) and (PDATAP,PDATAN) should be routed as balanced transmissions lines with a characteristic balanced impedance of between 80 to 120 . The two traces in the signal pair should be routed together and should be matched in length to within +/-3mm. The pairs of balanced line traces should be matched in length to within +/- 10mm. To save components, 100 termination resistors are embedded in the high speed subLVDS signal pairs (PCLKP/PCLKN) and (PDATAP/PDATAN) of the STV0974. All passive components for the STV0974 should be placed in close proximity to the device, including the decoupling capacitors. The decoupling capacitors for the VS6552 should be placed close to the sensor.
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8
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+VI/O EXTCLK POWERDOWN +VI/O PDATAP PDN PDATAN PCLKP PCLKN CLK DIO[0:7] DATA[0:7] HSYNC DIO8 Note 1 VSYNC DIO9 HCLK DIO10 DIO11 1.8V
4.7k
Application schematics
CLK
PDN PDATAP
1.8V 100 nF
VDD
PDATAN
PCLKP
VSYNC HCLK
VS6552 STV0974
Note 2 DIO12
DIO13 MSCL MSDA 1.8V
100 nF
PCLKN
Application schematics
2.8V 100 nF
AVDD
CEXT MSCL MSDA VDD x 6 VDDPOR
100 nF
SCL SDA
SCL SDA
GND
AGND
RST POR VSS x 11 VCORE 10nF
+VI/O
TCK
TDI TMS
Note: 1 Low level shifter reference: 74VCX1632245 For connection details, contact ST.
Figure 39: Mobile camera application, 8-bit parallel video interface, VI/O = 2.8V with low level shifter
STV0974
2 DIO12 can be used for flash mode
STV0974
EXTCLK POWERDOWN PDN PDATAP PDATAN PCLKP PCLKP PCLKN PDATAN DIO8 DIO9 DIO10 PDATAP PDN CLK DIO[0:7] RS CSN WRN DIO11 DIO12 1.8V
4.7k
CLK
DATA[0:7]
1.8V 100 nF
VDD
VS6552
PCLKN
2.8V 100 nF
AVDD
STV0974
RDN DRQ DIO13 IRQ
CEXT MSCL MSDA AGND
100 nF
100 nF MSCL MSDA 1.8V Cd
SCL SDA RST
GND
VDD x 6 VDDPOR
POR 10nF VSS x 11 VCORE
Figure 40: Mobile camera application, microprocessor interface, VI/O = 1.8V, no low level shifter
TCK
TDI TMS
Application schematics
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Evaluation kit and demonstration boards
STV0974
9
Evaluation kit and demonstration boards
A number of support kits are available. The evaluation kit is recommended for evaluation and system integration as it is an open system and electrical connections can be made from the EVK to the host system. The demonstration boards are small kits that do not allow hard connections to the customers system.
Table 46: Ordering details Part Number
STV-974-/552S-E01 STV-974/552S-R01 STV-974/552S-R02
Description
Evaluation kit including base board, STV0974 plug in, flex attached VS6552 plug-in and socketed VS6552 plug-in Demonstration board with flex attached VS6552 Demonstration board with socketed VS6552
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STV0974
Revision history
Revision history
Revision
0.1 0.2
Date
December 2003 January 2004
Comments
Product preview, draft 10 released in ADCS Update of application schematics to reflect the changes on some pin name for the VS6552. Update of some register default values.
1
April 2004
Description of video compression block in Functional description. Addition of Register Group 6 for flash mode (IC register map.) Review of register default values in IC register map. Review and update of device characteristics in Electrical characteristics
1 2
June 2004 28 Oct 2004
Minor revision. Updated cross reference to Table 35 Document status changed to datasheet to reflect the product maturity level. Changes applied:
Table 21: Timing constraints : t5 value changed to 7 s minimum (instead of 20s) Table 41: Video output timing (Figure 33) - Note 1 change capacitance value to 12pF( instead of 30 pF) Section 3: Signal description: Added precisions about internal resistor for PDATAP/N and PCLKP/N Electrical characteristics: Modified IDDP typical value 5 A (instead of 10). PCB layout guide lines for the STV0974 and VS6552: Added one sentence about embedded termination resistors in the STV0974.
3 23 Nov 2004 Minor revision. Format update.
References
[1] ITU-R Rec.BT.656-4. Interfaces for digital component video signals in 525-line and 625-line television system operating at the 4:2:2 level of recommendation ITU-R BT.601 (Part A), 19861992-1994-1995-1998 ITU-T Rec. T.81 (1992E) - ISO/IEC 10918-1:1993(E), Information Technology- Digital compression and Coding of Continuous-tone Still Images - Requirements and Guidelines
[2]
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STV0974
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics. All Rights Reserved. STMicroelectronics Group of Companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America http://www.st.com
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